#### Event Title

Constructing Rectangle Visibility Layouts for Rectangle Visibility Graphs

#### Presentation Type

Oral and/or Visual Presentation

#### Presenter Major(s)

Mathematics

#### Mentor Information

Feryal Alayont, alayontf@gvsu.edu

#### Department

Mathematics

#### Location

Kirkhof Center 2266

#### Start Date

13-4-2011 1:30 PM

#### End Date

13-4-2011 2:00 PM

#### Keywords

Mathematical Science, Technology

#### Abstract

In graph theory, a graph is a set of nodes and the connections between those nodes. We will look at graphs called Rectangle Visibility Graphs (RVGs), which are graphs that can be represented as a set of rectangles in the plane with connections represented by visibilities between rectangles. RVGs have an important application in VLSI chip design, where rectangle layouts can model the layout of a chip where components have a necessary set of connections. We will look at whether or not all graphs are RVGs, and then explore some of the ways rectangle visibility layouts can be constructed for a given graph where possible. A new algorithm for constructing rectangle layouts for certain graphs will be presented.

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Constructing Rectangle Visibility Layouts for Rectangle Visibility Graphs

Kirkhof Center 2266

In graph theory, a graph is a set of nodes and the connections between those nodes. We will look at graphs called Rectangle Visibility Graphs (RVGs), which are graphs that can be represented as a set of rectangles in the plane with connections represented by visibilities between rectangles. RVGs have an important application in VLSI chip design, where rectangle layouts can model the layout of a chip where components have a necessary set of connections. We will look at whether or not all graphs are RVGs, and then explore some of the ways rectangle visibility layouts can be constructed for a given graph where possible. A new algorithm for constructing rectangle layouts for certain graphs will be presented.