Implementation of a Software Transactional Memory System in Prolog

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Dr. Greg Wolffe, wolffe@gvsu.edu

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Practical limitations in power dissipation on computer chips have slowed manufacturers’ steady delivery of increases in clock speed, and consequently they have turned to delivering multiple CPU’s on most chips in order to keep up with industry’s appetite for increased performance. Multiple CPU’s readily increase performance for today’s multiple-application operating systems, but individual applications can benefit only if programmed to run in parallel. Transactional memory, which comes in hardware (HTM) and software (STM) varieties, purports to address some of the challenges that programmers face as they develop tomorrow’s parallel programs. Our goal was to implement a software transactional memory (STM) system in the Prolog language, and then to assess its utility, performance, scalability, usability, and benefits for code composability via the process of implementing three parallel programs. These assessments are qualitative and based on ability to implement the parallel programs, throughput, parallel speedup, comparisons between STM- and non-STM code versions, and an evaluation of the need for any special efforts required for STM-enabled code modules to interoperate. Our results demonstrate acceptable outcomes for the properties of interest. We show that while the impact on performance of the STM system is significant, its scalability, utility, usability, and benefits for code composability justify continued interest in the implemented STM system and in the STM paradigm.

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