Date Approved

8-19-2026

Graduate Degree Type

Thesis

Degree Name

Engineering (M.S.E.)

Degree Program

School of Engineering

First Advisor

Dr. Nabeeh Kandalaft

Second Advisor

Dr. Brian Krug

Third Advisor

Dr. Brian DeVries

Academic Year

2025/2026

Abstract

Virtualization has become an important methodology for implementing security and efficiency in embedded systems design. Virtualized environments provide flexibility and scalability of user-space environments, as hardware capabilities allow for multiple environments to run concurrently using the same hardware without impacting system performance or cost metrics. The ability to implement virtualized environments is fundamentally based on the instruction set architecture (ISA), which implements the necessary commands to facilitate the interface between physical hardware and virtual components.

RISC-V is an open-source ISA that can be used to generate platforms that support virtualization through the use of the H-Extension ISA. Previous research into developing a RISC-V platform with the H-Extension looked into the development of the Rocketchip softcore deploying seL4 as a microkernel and hypervisor to create a secure, virtualized environment. This effort has since become outdated, due to updates to the Rocketchip and H-Extension code-bases. Furthermore, the previous design was limited in scope to resources defined by existing components on the chosen development platform, the ZCU102.

This research describes an implementation of the Rocketchip RISC-V platform with updated H-Extension support. This effort will focus on the development of the physical platform, along with the development and testing of the H-Extension and seL4 as a viable hypervisor option on the new platform.

The result of this research is the initial design of a brand new Rocketchip platform variation that is board-agnostic in design approach whilst still maintaining support for seL4 and the H-Extension. This design will provide ample opportunities to explore the deployment of seL4 as a hypervisor solution on a multitude of FPGA platforms, and provide a large design space for a variety of different virtual platform configurations.

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