Date of Award


Degree Type


Degree Name

Engineering (M.S.E.)


School of Engineering


The purpose of this project was to fabricate a low noise N-type Metal-Oxide- Semiconductor (NMOS) imager in the Grand Valley State University (GVSU) Cleanroom with a focus on reducing pixel dark current. Previous research suggests Photodiode (PD) shape affects dark current and charge transfer characteristics of the pixel. Five PD shapes were designed to determine an optimized pixel shape with respect to dark performance. PN junction PDs with the Three Transistor (3T) pixel architecture were found to be the most suitable for imager fabrication in the GVSU cleanroom. The integrated circuit layout of several 8x8 pixel arrays was designed to test the influence of PD shape on dark current. The fabricated PDs exhibited dark current in the range of 9-18uA/cm2. The results indicate PDs with “rounder” geometry exhibit improved dark response; however, small saturation to cutoff current ratios prevented imager functionality. Improved charge transfer as a result of triangular PD shape was suggested but may have been masked by higher dark currents in these shapes.

A low noise Voltage and Sample and Acquisition Controller (VSAC) was developed to capture the output from the imager die and transfer the data to a computer. The VSAC was designed for flexible timing and voltage control while exhibiting low noise. Analysis with a logic analyzer verified timing flexibility which allowed the integration, reset, and other control pulses to be optimized for the application. Reset voltage control circuitry allowed a wide range of analog voltages to be supplied to the imager reset transistors. This prevented image lag due to incomplete reset. The noise performance of the VSAC was characterized by sampling a known voltage and observing the output deviation. With an output voltage accuracy of 99 percent to the input signal and less than 3.6 mVRMS output noise, the VSAC exhibited excellent low noise operation.

Included in

Engineering Commons