Date Approved


Graduate Degree Type


Degree Name

Engineering (M.S.E.)

Degree Program

School of Engineering

First Advisor

Dr. Chirag Parikh

Second Advisor

Dr. Jeffrey Ward

Third Advisor

Dr. Christian Trefftz


This paper compares Vivado High-Level Synthesis (HLS), a new mainstream technology offered by Xilinx Inc., against the typical Hardware Description Language (HDL) design approach. An example video filter application was implemented via both methods and compared for differences in performance and Non-Reoccurring Engineering (NRE). Lessons learned using HLS are also provided. The objective of this paper is to provide actual comparison data on the current state of mainstream HLS to enable informed decision making for designs considering HLS.

The Xilinx Zync System on a Chip (SoC) offering is used as a platform for both the traditional HDL methods and HLS. This platform includes Field Programmable Gate Array (FPGA) fabric combined with a high speed application microprocessor. These single silicon SoC solutions appear to be a platform capable of effectively utilizing HLS. The example video application selected for implementation is a 9 by 9 kernel convolution filter performed on 24 bit 1080p video at 60 frames per second. The 2013 Xilinx Vivado tool suite was used for both HLS and HDL methods.

HLS proved to be very easy to use to create a functional RTL design. With naïve implementations in both, HLS did not perform well in resource utilization. HLS also provided a design with a slower maximum clock frequency.

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Engineering Commons