seL4 on RISC-V – Developing High Assurance Platforms with Modular Open-Source Architectures
Location
Loosemore Auditorium
Description
PURPOSE: The purpose of this research was to port and evaluate the seL4 microkernel as a hypervisor on a RISC-V implementation of the Rocketchip that executes within FPGA fabric. SUBJECTS: The Rocketchip is a software generated implementation of a RISC-V processor that can execute in FPGA fabric. This study the Rocketchip to implement the draft specification for the RISC-V H-extension (v0.6.1). The H-extension extends the MMU within the Rocketchip to handle virtualization. METHODS AND MATERIALS: Chipyard is an opensource framework for defining, architecting, and configuring RISC-V based platforms to run on an FPGA. Once generated the Rocketchip was deployed and evaluated on the Xilinx ZCU102. The guest operating system, Linux, was then evaluated with system tools such as: stressing, cyclic-test, and perf. ANALYSES: The seL4 kernel, virtual machine monitor, and finally the guest operating system booted on the Rocketchip. RESULTS: These results of this study indicate that seL4 is a viable option to utilize on RISC-V for embedded virtualization. The reference architecture used in this design can serve as a basis for future implementation and evaluation of virtualized designs. CONCLUSIONS: This study provides the first public implementation of seL4 on RISC-V executing on the ZCU102 development platform. The processes and methods outlined in this can now serve as a reference when porting this architecture to a different platform; and to also serve as an additional tool when evaluating modifications to specification for the H-extension.
seL4 on RISC-V – Developing High Assurance Platforms with Modular Open-Source Architectures
Loosemore Auditorium
PURPOSE: The purpose of this research was to port and evaluate the seL4 microkernel as a hypervisor on a RISC-V implementation of the Rocketchip that executes within FPGA fabric. SUBJECTS: The Rocketchip is a software generated implementation of a RISC-V processor that can execute in FPGA fabric. This study the Rocketchip to implement the draft specification for the RISC-V H-extension (v0.6.1). The H-extension extends the MMU within the Rocketchip to handle virtualization. METHODS AND MATERIALS: Chipyard is an opensource framework for defining, architecting, and configuring RISC-V based platforms to run on an FPGA. Once generated the Rocketchip was deployed and evaluated on the Xilinx ZCU102. The guest operating system, Linux, was then evaluated with system tools such as: stressing, cyclic-test, and perf. ANALYSES: The seL4 kernel, virtual machine monitor, and finally the guest operating system booted on the Rocketchip. RESULTS: These results of this study indicate that seL4 is a viable option to utilize on RISC-V for embedded virtualization. The reference architecture used in this design can serve as a basis for future implementation and evaluation of virtualized designs. CONCLUSIONS: This study provides the first public implementation of seL4 on RISC-V executing on the ZCU102 development platform. The processes and methods outlined in this can now serve as a reference when porting this architecture to a different platform; and to also serve as an additional tool when evaluating modifications to specification for the H-extension.