Date Approved

8-2-2023

Graduate Degree Type

Thesis

Degree Name

Engineering (M.S.E.)

Degree Program

School of Engineering

First Advisor

Dr. Nabeeh Kandalft

Second Advisor

Dr. Chirag Parikh

Third Advisor

Dr. Byron Devries

Academic Year

2022/2023

Abstract

Virtualization is now becoming an industry standard for modern embedded systems. Modern embedded systems can now support multiple applications on a single hardware platform while meeting power and cost requirements. Virtualization on an embedded system is achieved through the design of the hardware-software interface. Instruction set architecture, ISA, defines the hardware-software interface for an embedded system. At the hardware level the ISA, provides extensions to support virtualization.

In addition to an ISA that supports hypervisor extensions it is equally important to provide a hypervisor completely capable of exploiting the benefits of virtualization for securing modern embedded systems. Currently there does not exist a commercial hardware design that leverages the RISC-V ISA hypervisor extension co-designed with an open-source microkernel.

This research describes an implementation of the seL4 open-source microkernel with the latest version of the RISC-V hypervisor extension (H-extension v0.6.1) specification in a Rocket chip soft core. The combination of open ISA, open-source OS and open-source hardware enables hardware and software co-design for securing embedded applications.

The implication of this research provides a meaningful evaluation of RISC-V with the seL4 open-source microkernel by providing an open-source hardware implementation on a Zynq Ultrascale+ MPSoC ZCU102 to assist the RISC-V community towards implementation and evaluation of hypervisor technology such as seL4.

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